QEMU uses a single-threaded tiny code generator (TCG) which translates instructions of the guest ISA to instructions of the host ISA. These translated instructions are then executed on the host in an execution thread. For SMP guests, this single thread is scheduled to execute translated instructions of all the CPUs in a round robin manner. This is a significant performance bottleneck in utilizing all the available cores on the host machine. Multi-threaded TCG (MTTCG) project was started to solve this problem by designing and implementing a multi-threaded TCG. In this design, multiple threads are concurrently scheduled, and each thread executes the translated instructions from one guest CPU. Various consistency issues were identified in this design and the current work aims to solve them.