HDMI (High-Definition Multimedia Interface) is a proprietary audio/video interface for transferring uncompressed video data and compressed or uncompressed digital audio data from an HDMI-compliant source device to an HDMI-compliant sink device. The Project deals with the creation of HDMI Source and Sink IP cores in Python Using MyHDL. These IP cores makes it easy for anyone to build a HDMI Transmitter and Receiver using FPGA. Python's power and clarity make MyHDL an ideal solution for high level modeling. The project will also serve as an useful example for the Python MyHDL project to show a non‐trivial example of an IP core.
RISC-V is an open ISA freely available for all types of use. The RISC-V ISA has been designed with small, fast, and low-power real-world implementations in mind, but without "over-architecting" for a particular microarchitecture style. The Project deals with the implementation of RISC-V processor in Python using MyHDL. The project demonstrates the advantages of MyHDL and Python in the field of CPU design.