The proposal is to design and test Gigabit Ethernet Media Access Controller (GEMAC) core in MyHDL using Python. The GEMAC is a communication core commonly used for streaming data coming from Transmitter and Receiver client interfaces to the FPGA. The purpose of the project is to create a design that can be easily used and understood by any endpoint user. This project proves the capability of MyHDL to create user friendly versions of hardware system designs. In this project we also develop a test suite to verify the functionality of the system design. This project is important because it demonstrates the use of advanced software technologies applied to hardware design.