Schematics are a great way to understand electronic circuits, and specially when we are using high level descriptions, it becomes essential that we are able to portray what we have in mind. Automatic schematic generation will allow us to generate publication quality schematics directly from HDLs (verilog in this case).
The objective is to take input a circuit desciption in json format (generated by yosys tools), and automagically create a schematic for it. The algorithm will run on the client side, so there will be no need to send data to server (thus no privacy concerns). Moreover interactivity with the generated circuit will allow it to be used as a great tool for learning circuits and HDL.
I plan to implement the core algorithm as library which can be easily extended to work with a variety of cases like
- Combining it with simulators to perform interactive simulations
- Using it to create non-electronic schematics