The main goal of the proposed project is to create the frontend part of a JPEG encoder which will be implemented in MyHDL. The frontend part consists of the color-space converter, the 2D DCT, the top-level FSM, and the input buffer. Based on a reference design, the final implementation in MyHDL will provide a more modular and scalable design. Throughout the project, will be developed all the required unit tests to prove the correct functionality of each block of the frontend part of the encoder while keeping in mind not only to verify the correct behavior of the design but also to produce synthesizable VHDL/Verilog code. The ideal goal would be to create a fully working JPEG encoder by combining the frontend and the backend part of the encoder written in MyHDL and implement the converted code in a FPGA board in order to measure some metrics like resource utilization and performance.