Leros is a tiny resource optimised open source microprocessor written in VHDL. The proposal is to reimplement Leros in MyHDL so that it can be used as an intelligent controller for various peripheral devices in Rhea designs, and compare it's performance on various FPGA boards, and demonstration through implementation of a command bridge state machine.

Student

Pranjal Agrawal

Mentors

  • Christopher
  • Oscar Diaz
  • Martin Schoeberl
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2016