Update riscv-sodor currently implemented in Chisel2 to Chisel3 along with that also update Privilege ISA Spec it complies to from 1.7 to 1.10 and then later port sodor to an FPGA using an AXI wrapper eventually allowing others to use Sodor (a librecore) in their projects. Updating sodor an educational microarchitecture to latest tools and specifications would help teach/convey latest standards.

Student

kritik bhimani

Mentors

  • Christopher Celio
  • Stefan Wallentowitz
close

2017