Contributor
Rahul Vyas

FPGA-realtime focus peaking


Mentors
Bertl
Organization
Apertus Association

The proposal describes detail description for the design of real time focus peaking kernel in VHDL for FPGA. It covers all aspects of the image processing required for FOCUS peaking namely, Demosaic interpolation, Sobel edge detection and edge thresholding for focus peaking.