Digital Filter Block Implementations in MyHDL and PyFDA Integration

Design and implementation of digital filters is essential for electronics engineers. Digital filter design in hardware usually is a two stage process; algorithm development in a language like Python, Matlab or Java and RTL design in a Hardware Description Language like VHDL or Verilog. myHDL is a Python module for developing, synthesizing and testing HDL code. PyFDA is a GUI based tool in written in Python/Qt for analysing and designing discrete time filters. This project aims to leverage and demonstrate the advantages of myHDL, PyFDA and python in general in the field of Digital Filter design. Algorithm exploration, modeling, designing and simulating of digital filters can all be done in Python and PyFDA. The project will focus on development and rigorous testing of digital filter designs and their integration with PyFDA. The algorithms for each type of filter will be chosen such that the hardware utilization is kept to a minimum. Initially Systolic FIR filter and parallel path IIR filter will be implemented. Later more complicated implementations of non-linear estimation filters will be explored. The filters will be rigorously tested and integrated with PyFDA.