WARP-V is an emerging open-source CPU core generator for RISC-V CPUs. It benefits from the flexibility of Transaction-Level Verilog (TL-Verilog) to support a wide range of implementations from simple CPUs for FPGAs through high-frequency ASIC implementations. The goal of the project is to formally verify the WARP-V core, making development easier for the strict requirements of the RISC-V specification and enabling the use of the WARP-V core in highly demanding and critical areas.

Student

Ákos Hadnagy

Mentors

  • Stefan Wallentowitz
  • Steven Hoover
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2018