A completely FOSS toolchain for FPGAs.

SymbiFlow is a group of projects aiming to dramatically broaden the outreach of FPGA platforms and lower entry barriers into FPGA development for both professional engineers and hobbyists by providing a completely FOSS flow for developing FPGA IP.

We believe FPGAs are an exciting and versatile development platform that could be used for addressing a variety of complex tasks, from flexible parallel I/O, through camera interfacing, low-latency machine learning, hardware glue logic to general hardware-accelerated parallel processing, in a much broader number of scenarios than today. A big roadblock to wider adoption are the specific tools that need to be learned on a per-vendor basis and their proprietary licensing.

By working to implement a vendor neutral and modular flow that is easy to integrate with various types of other tools, and more closely corresponds to a development experience known to the wider software development community ever since GCC was created, SymbiFlow is meant to drastically accelerate software-driven innovation in FPGA development.

SymbiFlow is already enabling new tools, development platforms and communities that build around the end-to-end open flow that is already working for some platforms. But there is still a lot of work ahead!

To achieve SymbiFlow's goal of a complete FOSS FPGA toolchain, a number of tools and projects are necessary to provide all the needed components of an end-to-end flow. Thus, SymbiFlow serves as an umbrella project for several activities, the central of which pertains to the creation of so-called FPGA "architecture definitions", i.e. documentation of how specific FPGAs work internally.

Those definitions and serve as input to open source backend tools like nextpnr and Verilog to Routing, and frontend tools like Yosys. They are created within separate collaborating projects targeting different FPGAs - Project X-Ray for Xilinx 7-Series, Project IceStorm for Lattice iCE40 and Project Trellis for Lattice ECP5 FPGAs.

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  • verilog
  • fpga
  • xilinx


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SymbiFlow 2019 Projects

  • Fahrican Koşar
    Optimization of VPR File Formats
    I propose replacing VPR’s XML reader for the architecture file with a schema-generated one. Furthermore, I propose replacing current rr_graph,...