QEMU's TCG just-in-time compiler translates target CPU instructions into host CPU instructions so that programs written for other CPU architectures can be run on any host. Modern CPUs feature vector processing instructions, sometimes called Single Instruction Multiple Data (SIMD) instructions, which perform the same operation on multiple data elements at once. Intel's SSE and AVX instruction set extensions were introduced for x86 CPUs for this purpose.

The target/i386 front-end has support for TCG emulation of SSE4.2, but does not feature support for later vector extensions, such as AVX. The goal of the proposed project is to implement and test AVX instructions that are currently not implemented in QEMU's TCG.



Jan Bobek


  • Richard Henderson