Analysis of the architectural performance of WARP-V using FireSim and RocketChip Chisel code. Adding WARP-V to RocketChip to utilize the capabilities of RocketChip in generating a whole SoC. Integrating WARP-V with RocketChip components: L1 Cache, TLB and Page table walker to make RocketChip, WARP-V version, able to run Linux. then running RocketChip, WARP-V version, on FireSim to analysis the performance of WARP-V.

Student

Alaa Salman

Mentors

  • Steven Hoover
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2019