Bidirectional Packet Protocol for FPGA Communication

Apertus-Axiom Beta utilizes two Lattice MachXO2s to expand the IOs interfaces for the main processing unit (ZYNQ-SoC). The channel comprises two LVDS pairs sharing a common clock with ZYNQ. The main idea behind designing a bidirectional packet protocol is to utilize the bandwidth efficiently and support various bus protocols on the MACHXO2 namely SPI, I2C and GPIO-based, ensuring predictable latency.