The goal of this project is to devise and implement a simulation-ready memory controller dedicated to benchmarking processor cores implemented on field programmable logic, that will produce delays much closer to a system where the memory interface is running at a much slower clock speed. This can take two forms.
- A simulation model for a memory controller that is tunable.
- A synthesizable module to be placed between the soft core implementation and an existing non-tunable DRAM controller.
Novelty and benefits to the community
So far, papers have been reluctant to provide accurate processor core performance figures extrapolated from FPGA implementation because DRAM controllers have an unrealistically high clock speed clock speed relatively to a soft core, compared to an ASIC core implementation. Providing the community with open source tunable memory controller models dedicated to the benchmarking of soft cores will greatly help producing more accurate and interpretable core and accelerator performance figures without requiring an ASIC tape-out in the first place, which is often not even an option.