I will focus on the Vehicle-to-Routing (VTR) component of the SymbiFlow project. Specifically, I will work on improving the existing electronic design automation (EDA) tools that place and route various logic gates, flip-flops, look-up tables (LUT) and more complex logic blocks on the Field-programmable Gate Array (FPGA). Important evaluation factors are the speed of the optimization process and the quality of the final mapped design.
Two major techniques that I will experiment with are:
- Providing a fast and decent preliminary placement solution that does not cluster remotely related logics.
- Allowing clusters to be taken apart and the primitives optimized during placement.