The WARP-V RISC-V core generator was developed in 2018, it is the most-configurable, most-adaptable open-source RISC-V CPU core generator, taking advantage of advanced digital design features of TL-Verilog. Till now WARP-V has support for RV32I base instruction set architecture and is formally verified using Risc-V formal. My proposal is to implement RV32F(Single Precision Floating-point) Unit extensions to the Warp-V core by using a "hard float by Berkeley" library written in chisel, which also supports IEEE 754 single-precision floating-point unit. My proposal is also to introduce Virtual Memory support(TLB) in Warp-V and to complete the implementation of Bit-Manipulation Instructions.

Student

VineetJain07

Mentors

  • Steve Hoover
  • Ákos Hadnagy
close

2020