The goal of the project is to automate and augment the verification of the custom FPGA and the bitstream with Cocotb, an open-source framework for verifying VHDL/ Verilog RTL using python. At the end of the project, users will get to generate a bitstream file and also know whether it is correct or not automatically.

Student

Ansh Puvvada

Mentors

  • Jonathan Balkind
  • Ang Li
  • Stefan Wallentowitz
close

2020