WARP-V is an open-source and highly flexible and configurable CPU core with customisable ISA and pipelines written in the emerging “Transaction-Level” modelling. OpenPiton is an open-source, general-purpose, multi-threaded manycore framework for heterogeneous architecture research. This project aims to evolve WARP-V further by adding necessary support for memory, microarchitecture extensions etc., and make it RISC-V Linux compatible and then integrate it with the OpenPiton-derived Bring Your Own Core (BYOC) Framework. This would open the doors for the first Linux-capable processor based on TL-Verilog and easy scaling to multicore heterogeneous implementation with OpenPiton.

Student

Shivam Potdar

Mentors

  • Jonathan Balkind
  • Steve Hoover
  • Ákos Hadnagy
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2020