The VTR (Verilog-to-routing) project provides an academic open-source CAD flow for FPGAs, combining tools for Synthesis and Logic Optimization (Yosys, ODIN, ABC), with tools for physical implementation (VPR). At the heart of this tool suite, is a set of scripts that manage the execution of coordinate of these tools. Currently, these scripts are written in a few different languages, but mostly in Perl. I am proposing converting the Verilog-to-routing test runner scripts from Perl to Python. While doing this I will make various optimizations and enhancements.

Organization

Student

Shad Torrie

Mentors

  • Jeff Goeders
close

2020