CHIPS Alliance

Open source IP, tools & standards for ASIC/FPGA

Technologies
fpga, chisel, risc-v, systemverilog, ASIC
Topics
soc, IP cores, ASIC design, HDL, chiplets
Open source IP, tools & standards for ASIC/FPGA
CHIPS Alliance develops high-quality, open source hardware components and tooling for silicon devices and FPGAs. By creating an open and collaborative environment, shared infrastructure, processes, legal support and governance, CHIPS Alliance shares resources to lower the cost of development and increase confidence in high-quality open source building blocks it helps manage. Within CHIPS Alliance's workgroups covering areas such as Analog, FPGA, ASIC design tools, Chisel, Interconnects and Cores, companies and individuals can work together to develop open source IP, tools and standards. CHIPS Alliance is open to all organizations who are interested in collaborating on open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.
2022 Program

Successful Projects

Contributor
Karim Tera
Mentor
tgorochowik
Organization
CHIPS Alliance
Verible SystemVerilog Preprocessor
The objective is to create a SystemVerilog preprocessor for Verible (which is a suite of SystemVerilog developer tools, including a parser,...
Contributor
Lucca Silva
Mentor
msaligane
Organization
CHIPS Alliance
Improving the automatic layout generation of the mixed-signal temperature sensor block in OpenFASOC
OpenFASOC is an open-source framework for autonomous generation of optimized integrated circuit blocks given user specifications. It is a growing...
Contributor
saicharan00112
Mentor
msaligane
Organization
CHIPS Alliance
Development of a smart CI workflow to test analog block functionality and performance in OpenFASOC
OpenFASOC, an automated SOC generator, is enabling chip enthusiasts to develop circuits/macros with a software approach. Circuits must not only be...