1st CLaaS for PYNQ FPGAs
- Mentors
- Steve Hoover, Theodore Omtzigt
- Organization
- Free and Open Source Silicon Foundation
- Technologies
- python, verilog, bash, tcl, TL-Verilog, Zynq FPGA, Pynq
- Topics
- fpga, Hardware Accelerators, Electronic Design Automation, Custom Logic as a Service, Remote FPGA development framework
Utilizing cloud FPGAs prove to be very expensive and minor coding bugs could consume precious compute cycles and incur hefty bills. This proves using FPGAs on AWS F1, virtually ineffective for students, enthusiasts and early researchers. Additionally, 1st CLaaS, already has a streaming interface in place, not all hardware accelerators would require continuous streaming of data. The addition of support for Memory Mapped Interfaces like AXI4, AXI4 Lite, Wishbone and custom interfaces similar to RoCC, Core-V eXtension interface etc., would enable a wider ecosystem of hardware accelerators to support 1st CLaaS integration without any RTL Level modifications.
Besides these, supporting 1st CLaaS on Local FPGAs/Remote FPGAs contrary to AWS F1 would prove useful to enthusiasts, researchers, professors and students having FPGA on-premise or remotely accessible. 1st CLaaS for PYNQ leverages the PYNQ (Python Productivity for Zynq) Framework, which consists of a Jupyter Server running in a Linux Operating system on the ARM Processor in the Zynq SoC. Addressing the current limitations of 1st CLaaS, the proposed framework that not only brings 1st CLaaS to PYNQ FPGAs, but also vendor agnostically automates TL-Verilog/Verilog/SystemVerilog based Hardware accelerator design from RTL to bitstream and deployment eliminating the need to interact with a wide range of vendor specific tools. The framework would provide a complete FPGA based hardware design flow within the browser/terminal right from designing in makerchip-app and IP-Block design-Bitstream generation to deployment on FPGA in a single command.