Verible SystemVerilog Preprocessor

The objective is to create a SystemVerilog preprocessor for Verible (which is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter). Verible was created to handle un-preprocessed files, meaning that the parser's grammar handles the preprocessor directives in a limited way, e.g. macros are not expanded. A proper preprocessor is a must have in many cases, for example when a macro defined body doesn't add up to a non-terminal in the parser's grammar, in this case the un-preprocessed code doesn't make sense. Verible currently contains a pseudo-preprocessor tool, which have a flag option to filter out comments. A decoupled design between the lexer and parser will help us feed the lexed tokens to the preprocessor, then back to the parser. Deliverables: 1) Modified parser (removed preprocessor directives handling from grammar). 2) Well defined methods added the preprocessor class to handle the directives as described in SV 2017 LRM. 3) Each new feature is added to the standalone preprocessor tool as well.