TinyParrot: A minimal BlackParrot RISC-V Multicore variant
- Mentors
- Olof Kindgren, Dan Petrisko, Mark Wyse
- Organization
- Free and Open Source Silicon Foundation
- Technologies
- risc-v, systemverilog, Verilator, Computer architecture
- Topics
- ASICs, Minimal multicore, low resource tapeout, host processor, Linux-capable
This project aims to shrink BlackParrot multicore to have a minimal variant called TinyParrot multicore. The main goal of this project is to get very low resource ASIC tapeouts.
The deliverables of this project are:
**Provide Minimal ISA support: This will be done by parameterizing the FPU logic (all the FP
pipes, register file, and bypass paths).
**Shrink the size of caches: The cache size will be reduced to 1kb of data.
**Logic saving optimizations: The optimizations are planned to be done through Yosys. Yosys
supports optimization passes and runs them while synthesis.