Enhancing OpenPiton+Ariane With a High-Performance Data Cache

As the demand for High-Performance Computing (HPC) continues to grow, there is a need for open-source solutions that can deliver the performance required by modern applications. Different open-source architecture frameworks have been developed by the community, like OpenPiton, however, all of them present performance limitations that impact their ability to execute computationally-intensive tasks. OpenPiton is an open-source framework for designing many-core processors. Although OpenPiton was originally developed for SPARC v9 architectures, currently it is also compatible with different core architectures (RISC-V 32-bit, RISC-V 64-bit, x86, and SPARCv9). In this project, we will focus on improving the performance of the integration of CVA6/Ariane into OpenPiton (OpenPiton+Ariane). The architecture of OpenPiton consists of one chipset and one or more tiles. The chipset houses modules used to communicate the tiles with the peripherals, such as the UART. The tile is used to build the mesh for many-core designs. In these designs, the tiles are interconnected by three NoC routers to generate the mesh. Each tile comprises the three NoC routers, the Ariane core, and the cache hierarchy, which consists of Ariane’s private L1 data and instruction caches, a private L1.5 cache and a shared distributed L2 cache. Despite the fact that OpenPiton offers many advantages, it presents performance limitations that restrict its adoption in the HPC field. In this project, we will improve the performance of OpenPiton by replacing the L1 data cache of Ariane with the High-Performance, Multi-Requester, Out-of-Order, L1 data cache (HPDcache). In addition, other features such as the amount of L1.5 cache miss status holding registers (MSHRs) or the L1.5 cache associativity can also be improved in order to approach OpenPiton even closer to the HPC field.