Improving SDF support in Icarus Verilog

When you design a digital circuit, you want to make sure that all timings are correct, even post-layout. Therefore, the gate level netlist is annotated with delays extracted from the layout. The file format that contains these delay and timing information is called Standard Delay Format (SDF). Icarus Verilogs' SDF implementation has shortcomings in the following categories: 1. Wire / Interconnect delays 2. Conditional path delays 3. Timing checks Work needs to be done on these categories, all while supporting related bugs as we more completely test gate level simulations. With the work proposed here, I would like to improve Icarus' SDF support to simulate SDF back-annotated timing simulations for the open SKY130 PDK. The deliverables for this project are: 1. Implementing the SDF `INTERCONNECT` feature 2. Writing tests for the regression suite 3. Example of a SDF back-annotated timing simulation using the SKY130 PDK