Implementation of a Common Python Framework for OpenFASoC Generators

OpenFASoC is a project focused on creating fully automated user specifications to GDS generation flow using open-source tools. OpenFASoC uses tools such as OpenROAD, Yosys, Magic, and Netgen to fully autonomously choose the best parameters from the user specification and generate and simulate circuit blocks that could be used in SoCs. OpenFASoC was inspired by FASoC, which was built on proprietary tools. This project aims to replace the design-dependent Verilog generation and simulation runners with a common Python module that would be used across all generators with a consistent and simple Mako-based templating syntax for both Verilog and SPICE templates.