Makerchip Flows: A Suite of EDA Flow integrations for TL-Verilog ecosystem
- Mentors
- Steve Hoover
- Organization
- CHIPS Alliance
- Technologies
- python, verilog, fpga, make, bash, System Verilog
- Topics
- fpga, eda, Hardware Design
Makerchip Flows aims at developing EDA flows for TL-Verilog leveraging Edalize backend, for open source tools/flows like yosys, Openlane, F4PGA, Silicon Compiler, and also commercial ASIC Synthesis and Simulation tools. The project involves developing Flows with TL-Verilog (Makerchip IDE or SandPiper-SaaS) and integrating them into the website or use as a standalone flow. This involves developing support for tools and creating flows in Edalize. This effort Makerchip Flows also extends to adding TL-Verilog frontend for Silicon Compiler. This wide range of support and ecosystem developments will make TL-Verilog and its ecosystem the go-to for Design, Simulations, FPGA visualizations, and other explorations just within the browser, creating a low cost and low barrier to entry for beginners and engineers.