DSP hard block integration in F4PGA
- Mentors
- Maciej Kurc
- Organization
- CHIPS Alliance
- Technologies
- python, verilog, c++, Vivado, Yosys
- Topics
- fpga, IP cores, HDL
F4PGA is an open-source FPGA toolchain designed as a free alternative to proprietary computer-aided design tools like Xilinx’s Vivado. Currently, mapping designs to DSP blocks and generating DSP block bitstreams are not implemented for the Xilinx 7-series FPGA devices within the toolchain. This project aims to integrate DSP48E hard block in F4PGA. This will enable designs using DSPs to be synthesized, placed, and routed correctly. We need to diagnose and implement required changes throughout the F4PGA toolchain, allowing for DSP design bitstreams to be successfully generated with open-source tools. Deliverables: 1. Support for DSP48E within the F4PGA architecture definitions. 2. Testing flow for designs using Xilinx 7-series DSP hard blocks which include Verilog-to-Bitstream using the F4PGA toolchain, Fasm2bels to re-generate the original netlist from the bitstream output of F4PGA and Proof-test through Vivado to verify the correctness of the netlist.