Support Zvk in T1 (RISC-V Vector coprocessor)
- Mentors
- Jiuyang Liu, ZW YE
- Organization
- CHIPS Alliance
- Technologies
- chisel, risc-v, Scala Functional Programming, Spike, RTL Designing, Rocket Chip
- Topics
- research, documentation, computer architecture, cryptography, RISC-V, SIMD, RTL Designing, Vector Processing
Our "Support Zvk in T1" project aims to upgrade the T1 processor by adding Zvk, a cryptographic feature from the RISC-V architecture, enhancing its data processing and security capabilities. We'll start with researching how Zvk can fit into the T1's design, then move on to detailed planning and design. The heart of the project is the RTL design and implementation, where we'll turn our plans into a functional model. Testing ensures everything works perfectly, leading to the development of a demo application to showcase the new features. Documentation throughout will provide a blueprint for future advancements. This enhancement will not only improve the T1 processor's performance but also its ability to securely handle data, setting a new standard in the field.