Transforming the OpenHW High Performance Data Cache into a High Performance Instruction Cache
- Mentors
- Jonathan Balkind, César Fuguet, Noelia Oliete Escuín
- Organization
- Free and Open Source Silicon Foundation
- Technologies
- verilog, risc-v, systemverilog
- Topics
- computer architecture
Since CVA6/Ariane is highly modular by design, it is relatively easy to develop and integrate multiple L1 caches. Additionally, because CVA6/Ariane is open source, users can develop L1 caches customized for their needs.
The primary technological feature of HPDC is its L1 Dcache, which supports Multi-Requester, Multi-Issue, and Out-of-Order operations. This capability is especially valuable for HPC systems striving for high memory throughput. However, HPDC is still under development, and various functional enhancements are being implemented or planned to make it more useful for HPC systems by providing a variety of functions for diverse cores.
In this year's GSoC, the objective is to first expand the functionality of the L1 cache for the CVA6/Ariane core, and then to make it scalable to accommodate many cores, laying the groundwork for making HPDC an even more significant entity for HPC systems.
By exploring the appropriate scale and structure, it's possible to enhance HPDC's functions to be used as an instruction cache with scalability in mind. Furthermore, by connecting with OpenPiton, it becomes extremely easy to scale to large systems with many cores. This aligns with the goals of the GSoC project.