MyHDL : RISC-V Implementation

RISC-V is an open ISA freely available for all types of use. The RISC-V ISA has been designed with small, fast, and low-power real-world implementations in mind, but without "over-architecting" for a particular microarchitecture style.

The RISC-V being a base ISA is carefully restricted to a minimal set of instructions sufficient to provide a reasonable target for compilers, assemblers, linkers, and operating systems (with additional supervisor level operations), and so provides a convenient ISA and software toolchain skeleton around which more customized processor ISAs can be built. This project thus aims to leverage and demonstrate the advantages of myHDL and python in general in the field of CPU design by implementing a RISC-V CPU (in myHDL) and other CPU design utilities. Since RISC-V is a base ISA, having a myHDL based implementation becomes a essential and would enable a lot of Computer Architecture researchers to design and test RISC-V based derivatives using myHDL and python based utilities.