Low-latency I/O RISC-V CPU core in FPGA fabric

On several BeagleBone boards, there are an ultra-low latency 32-bit RISC CPUs called Programmable Real-time Units (PRUs) with register-mapped I/O directly to pins that is a custom architecture. The programmable nature of the PRU, along with its access to pins, events, and all SoC resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of the system-on-chip (SoC). To provide the capability of a Programmable Real-time Unit Industrial Control SubSystem (PRU-ICSS), I propose to deploy an existing RISC-V 32IM core with a customized Instruction Set Architecture on FPGA Fabric present on BeagleV-Fire. The goal of this deployment is to provide high bandwidth between the CPU and I/O, resulting in a on-board microcontroller. At project conclusion, BeagleV-Fire will host a fully functional PRU system that can execute Risc-V based instructions, and can be controlled by invoking specific functions within a C code using a PRU C library.