Improving ATPG Fault Coverage in Fault

The semiconductor industry, driven by Moore's Law, continuously pushes the boundaries of integrated circuit (IC) technology, leading to ever-shrinking transistor feature sizes. Recent research by the U.S. Department of Energy (U.S. DOE) shows promising endeavors of reducing feature sizes to record sizes as small as 1 nanometer. However, the growing complexity of ICs raises the likelihood of manufacturing defects, consequently, sustaining reliability within this zero-failure tolerance domain poses an increasingly daunting task. In this landscape, Design-for-Testability (DFT) features play a paramount role in guaranteeing the quality and reliability of integrated circuits (ICs) amidst evolving complexities. This proposal aims to enhance the Fault DFT toolchain through the Google Summer of Code (GSoC) program. “Fault” is a premier open-source DFT toolchain that provides a comprehensive solution including automatic test pattern generation (ATPG), scan insertion, and scan chain testing. The project focuses on improving Automatic Test Pattern Generation (ATPG) fault coverage within the Fault framework by integrating algorithmic ATPG methodologies and implementing techniques for enhancing controllability and observability in digital designs. By addressing these challenges, the project seeks to advance open-source EDA tools and meet the evolving demands of the semiconductor industry.